Z123003 12.3 Inch TFT LCD Display 1920*720 50PIN LVDS 400nits Full View

1

Display Size (Diagonal)

12.3

inch

2

Display Resolution

1920 (H) × RGB × 720 (V）

pixels

3

Pixel Pitch

152.1(H)× 152.1 (V）

um

4

LCM Outline Dimension

(Without FPC）

321.6 (W) ×138.8 (H) ×6.15 (T)

mm

5

LCD Active Area

292.032 (W) ×109.512 (H）

mm

6

View Direction (Gray Inversion)

FULL VIEW

-

7

Driver IC

/

-

8

Pixel Arrangement

RGB-Stripe

-

9

Display Mode

Normal Black

-

10

Pixel Driving Element

a-Si TFT

-

11

LCD Transmittance

Typ.: TBD

-

12

LCD Contrast Ratio

Typ.: 1100; Min:900

-

13

FPC Version

Z123003-P50 V1

-

14

Interface

LVDS

-

15

Operating Temperature

-20°C~ 70°C

-

16

Storage Temperature

-30°C~ 80°C

-

17

Backlight Arrangement

LED/4 Series 11 Parallel (44 lights in total)

-

18

Luminance

Typ.: 400

nit

19

Weight

0.515

kg

1

GND

Ground

2

NC

No connect

3-4

VCC

Panel Power

5-6

GND

Ground

7-8

NC

No connect

9

GND

Ground

10

O_IN0-

Odd pixel negative LVDS differential clock input

11

O_N0+

Odd pixel positive LVDS differential clock input

12

O_IN1-

Odd pixel negative LVDS differential clock input

13

O_N1+

Odd pixel positive LVDS differential clock input

14

O_IN2-

Odd pixel negative LVDS differential clock input

15

O_N2+

Odd pixel positive LVDS differential clock input

16

O_CK-

Odd pixel negative LVDS differential clock input

17

O_CK+

Odd pixel positive LVDS differential clock input

18

O_IN3-

Odd pixel negative LVDS differential clock input

19

O_N3+

Odd pixel positive LVDS differential clock input

20

E_IN0-

Even pixel negative LVDS differential clock input

21

E_N0+

Even pixel positive LVDS differential clock input

22

E_IN1-

Even pixel negative LVDS differential clock input

23

E_N1+

Even pixel positive LVDS differential clock input

24

E_IN2-

Even pixel negative LVDS differential clock input

25

E_N2+

Even pixel positive LVDS differential clock input

26

E_CK-

Even pixel negative LVDS differential clock input

27

E_CK+

Even pixel positive LVDS differential clock input

28

E_IN3-

Even pixel negative LVDS differential clock input

29

E_N3+

Even pixel positive LVDS differential clock input

30

GND

Ground

31

NC

No connect

32

RESET

Global reset pin, active low.

33

STBYB

Standby mode, active low.

34

CA3

Output signal to indicate self protection mode, when DE, HS, VS, DCLK, any of these signals is missing,

it will become High. If using this pin, CA3 need to pulled low by an resistor, else, let it floating.

35

SCL

Serial interface clock input. (User folating)

36

SDA

Serial interface data input/output. (User folating)

37

CSB

Serial interface chip enable. (User folating)

38-39

GND

Ground

40

NC

No connect

41-43

LEDA

BL Anode

44

NC

No connect

45-48

LEDK

BL Cathode

49

NTC_A

NTC_Anode

50

NTC_K

NTC_Cathode

RESET voltage should be consistent with VDDI voltage, or there probably is black screen fault when power on.